? 2002 fairchild semiconductor corporation ds500169 www.fairchildsemi.com may 1999 revised july 2002 gtlp18t612 18-bit lvttl/gtlp universal bus transceiver gtlp18t612 18-bit lvttl/gtlp universal bus transceiver general description the gtlp18t612 is an 18-bit universal bus transceiver which provides lvttl to gtlp signal level translation. it allows for transparent, latched and clocked modes of data transfer. the device provides a high speed interface for cards operating at lvttl logic levels and a backplane operating at gtlp logic levels. high speed backplane operation is a direct result of gtlp?s reduced output swing ( < 1v), reduced input threshold levels and output edge rate control. the edge rate control minimizes bus settling time. gtlp is a fairchild semiconductor derivative of the gun- ning transistor logic (gtl) jedec standard jesd8-3. fairchild?s gtlp has internal edge-rate control and is pro- cess, voltage, and temperature (pvt) compensated. its function is similar to btl or gtl but with different output levels and receiver thresholds. gtlp output low level is less than 0.5v, the output high is 1.5v and the receiver threshold is 1.0v. features bidirectional interface between gtlp and lvttl logic levels designed with edge rate control circuitry to reduce out- put noise on the gtlp port v ref pin provides external supply reference voltage for receiver threshold adjustibility special pvt compensation circuitry to provide consis- tent performance over variations of process, supply volt- age and temperature ttl compatible driver and control inputs designed using fairchild advanced bicmos technology bushold data inputs on a port to eliminate the need for external pull-up resistors for unused inputs power up/down and power off high impedance for live insertion open drain on gtlp to support wired-or connection flow through pinout optimizes pcb layout d-type flip-flop, latch and transparent data paths a port source/sink ? 24ma/ + 24ma b port sink + 50ma also packaged in plastic fine-pitch ball grid array (fbga) ordering code: note 1: ordering code ? g ? indicates trays. note 2: device also available in tape and reel. specify by appending suffix letter ? x ? to the ordering code. order number package number package description GTLP18T612G (note 1)(note 2) bga54a 54-ball fine-pitch ball grid array (fbga), jedec mo-205, 5.5mm wide gtlp18t612mea (note 2) ms56a 56-lead shrink small outline package (ssop), jedec mo-118, 0.300" wide gtlp18t612mtd (note 2) mtd56 56-lead thin shrink small outline package (tssop), jedec mo-153, 6.1mm wide
www.fairchildsemi.com 2 gtlp18t612 connection diagrams pin assignments for ssop and tssop pin assignments for fbga (top thru view) pin descriptions fbga pin assignments pin names description oeab a-to-b output enable (active low) (lvttl level) oeba b-to-a output enable (active low) (lvttl level) ceab a-to-b clock/le enable (active low) (lvttl level) ceba b-to-a clock/le enable (active low) (lvttl level) leab a-to-b latch enable (transparent high) (lvttl level) leba b-to-a latch enable (transparent high) (lvttl level) v ref gtlp input threshold reference voltage clkab a-to-b clock (lvttl level) clkba b-to-a clock (lvttl level) a1 ? a18 a-to-b data inputs or b-to-a 3-state outputs b1 ? b18 b-to-a data inputs or a-to-b open drain outputs 123 4 56 a a 2 a 1 oeab clkab b 2 b 1 b a 4 a 3 leab ceab b 4 b 3 c a 6 a 5 v cc v cc b 6 b 5 d a 8 a 7 gnd gnd b 8 b 7 e a 10 a 9 gnd gnd b 10 b 9 f a 12 a 11 gnd gnd b 12 b 11 g a 14 a 13 v cc v ref b 14 b 13 h a 16 a 15 oeba ceba b 16 b 15 j a 18 a 17 leba clkba b 18 b 17
3 www.fairchildsemi.com gtlp18t612 functional description the gtlp18t612 is an 18 bit registered transceiver con- taining d-type flip-flop, latch and transparent modes of operation for the data path. data flow in each direction is controlled by the clock enables (ceab and ceba ), latch enables (leab and leba), clock (clkab and clkba) and output enables (oeab and oeba ). the clock enables (ceab and ceba ) and the output enables (oeab and oeba ) control the 18 bits of data for the a-to-b and b-to-a directions respectively. for a-to-b data flow, when ceab is low, the device oper- ates on the low-to-high transition of clkab for the flip- flop and on the high-to-low transition of leab for the latch path. that is, if ceab is low and leab is low the a data is latched regardless as to the state of clkab (high or low) and if leab is high the device is in trans- parent mode. when oeab is low the outputs are active. when oeab is high the outputs are high impedance. the data flow of b-to-a is similar except that ceba , oeba , leba, and clkba are used. truth table (note 3) note 3: a-to-b data flow is shown. b-to-a data flow is similar but uses oeba , leba, clkba, and ceba . note 4: output level before the indicated steady state input conditions were established, provided that clkab was high before leab went low. note 5: output level before the indicated steady-state input conditions were established. logic diagram inputs output mode ceab oeab leab clkab a b x h x x x z latched lll hxb 0 (note 4) storage lll lxb 0 (note 5) of a data x l h x l l transparent xlh xhh lll l l clocked lll hh storage of a data hll xxb 0 (note 5) clock inhibit
www.fairchildsemi.com 4 gtlp18t612 absolute maximum ratings (note 6) recommended operating conditions (note 8) note 6: absolute maximum continuous ratings are those values beyond which damage to the device may occur. exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. functional operation under absolute maximum rated conditions in not implied. note 7: i o absolute maximum rating must be observed. note 8: unused inputs must be held high or low. dc electrical characteristics over recommended operating free-air temperature range, v ref = 1.0v (unless otherwise noted). supply voltage (v cc ) ? 0.5v to + 4.6v dc input voltage (v i ) ? 0.5v to + 4.6v dc output voltage (v o ) outputs 3-state ? 0.5v to + 4.6v outputs active (note 7) ? 0.5v to v cc + 0.5v dc output sink current into a port i ol 48 ma dc output source current from a port i oh ? 48 ma dc output sink current into b port in the low state, i ol 100 ma dc input diode current (i ik ) v i < 0v ? 50 ma dc output diode current (i ok ) v o < 0v ? 50 ma v o > v cc + 50 ma esd performance > 2000v storage temperature (t stg ) ? 65 c to + 150 c supply voltage v cc /v ccq 3.15v to 3.45v bus termination voltage (v tt ) gtlp 1.47v to 1.53v v ref 0.98v to 1.02v input voltage (v i ) on a port and control pins 0.0v to 3.45v on b port 0.0v to 3.45v high level output current (i oh ) a port ? 24 ma low level output current (i ol ) a port + 24 ma b port + 50 ma operating temperature (t a ) ? 40 c to + 85 c symbol test conditions min typ max units (note 9) v ih b port v ref + 0.05 v tt v others 2.0 v il b port 0.0 v ref ? 0.05 v others 0.8 v ref gtlp (note 10) 1.0 v gtl 0.8 v ik v cc = 3.15v i i = ? 18 ma ? 1.2 v v oh a port v cc , v ccq = min to max (note 11) i oh = ? 100 av cc ? 0.2 v v cc = 3.15v i oh = ? 8 ma 2.4 i oh = -24ma 2.0 v ol a port v cc , v ccq = min to max (note 11) i ol = 100 a0.2 v v cc = 3.15v i ol = 24ma 0.5 b port v cc = 3.15v i ol = 40 ma 0.40 v i ol = 50 ma 0.55 i i control pins v cc = min to max (note 11) v i = 3.45v or 0v 5 a a port v cc = 3.45v v i = 0v ? 10 a v i = 3.45 10 b port v cc = 3.45v v i = v cc 5 a v i = 0 ? 5 i off a port and control pins v cc = 0v i or v o = 0 to 3.45v 30 a i i(hold) a port v cc = 3.15v v i = 0.8v 75 a v i = 2.0v ? 75 i ozh a port v cc = 3.45v v o = 3.45 10 a b port v o = 1.5v 5 i ozl a port v cc = 3.45v v o = 0v ? 10 a b port v o = 0.55v ? 5 i cc a or b ports v cc = 3.45v outputs high 30 40 ma (v cc /v ccq )i o = 0 outputs low 30 40 v i = v cc or gnd outputs disabled 30 45
5 www.fairchildsemi.com gtlp18t612 dc electrical characteristics (continued) note 9: all typical values are at v cc = 3.3v, v ccq = 3.3v, and t a = 25 c. note 10: gtlp v ref and v tt are specified to 2% tolerance since signal integrity and noise margin can be significantly degraded if these supplies are noisy . in addition, v tt and rterm can be adjusted beyond the recommended operating conditions to accommodate backplane impedances other than 50 ? , but must remain within the boundaries of the dc absolute maximum ratings. similarly v ref can be adjusted to optimize noise margin. note 11: for conditions shown as min or max, use the appropriate value specified under recommended operating conditions. note 12: this is the increase in supply current for each input that is at the specified ttl voltage level rather than v cc or gnd. ac operating requirements over recommended ranges of supply voltage and operating free-air temperature, v ref = 1.0v (unless otherwise noted). symbol test conditions min typ max units (note 9) ? i cc a port and v cc = 3.45v, one input at 2.7v 0 2 ma (note 12) control pins a or control inputs at v cc or gnd c i control pins v i = v cc or 0 6 a port v i = v cc or 0 7.5 pf b port v i = v cc or 0 9.0 symbol test conditions min max unit f max maximum clock frequency 175 mhz t width pulse duration leab or leba high 3.0 ns clkab or clkba high or low 3.0 t su setup time a before clkab 1.1 ns b before clkba 3.0 a before leab 1.1 b before leba 2.7 ceab before clkab 1.2 ceba before clkba 1.4 t hold hold time a after clkab 0.0 ns b after clkba 0.0 a after leab 0.8 b after leba 0.0 ceab after clkab 1.0 ceba after clkba 1.9
www.fairchildsemi.com 6 gtlp18t612 ac electrical characteristics over recommended range of supply voltage and operating free-air temperature, v ref = 1.0v (unless otherwise noted). c l = 30 pf for b port and c l = 50 pf for a port. note 13: all typical values are at v cc = 3.3v, and t a = 25 c. extended electrical characteristics over recommended ranges of supply voltage and operating free-air temperature v ref = 1.0v (unless otherwise noted). c l = 30 pf for b port and c l = 50 pf for a port. note 14: t oshl /t oslh and t ost - output to output skew is defined as the absolute value of the difference between the actual propagation delay for all output s within the same packaged device. the specifications are given for specific worst case v cc and temperature and apply to any outputs switching in the same direction either high-to-low (t oshl ) or low-to-high (t oslh ) or in opposite directions both hl and lh (t ost ). this parameter is guaranteed by design and statistical process distribution. actual skew values between the gtlp outputs could vary on the backplane due to the loading an d impedance seen by the device. note 15: t pv - part to part skew is defined as the absolute value of the difference between the actual propagation delay for all outputs fr om device to device. the parameter is specified for a specific worst case v cc and temperature. this parameter is guaranteed by design and statistical process distribution. actual skew values between the gtlp outputs could vary on the backplane due to the loading and impedance seen by the device. note 16: due to the open drain structure on gtlp outputs t ost and t pv(lh) in the a-to-b direction are not specified. skew on these paths is dependent on the v tt and r t values on the backplane. symbol from to min typ max unit (input) (output) (note 13) t plh ab2.14.16.3 ns t phl 1.0 2.7 4.4 t plh leab b 2.2 4.2 6.3 ns t phl 1.0 2.4 4.2 t plh clkab b 2.2 4.4 6.5 ns t phl 1.0 2.5 4.4 t plh oeab b 2.0 3.8 5.6 ns t phl 1.0 2.6 4.3 t rise transition time, b outputs (20% to 80%) 3.1 ns t fall transition time, b outputs (20% to 80%) 2.1 t plh ba1.83.85.8 ns t phl 1.8 3.8 5.8 t plh leba a 0.3 2.2 4.6 ns t phl 0.4 2.4 4.6 t plh clkba a 0.5 2.4 4.6 ns t phl 0.6 2.6 4.6 t pzh , t pzl oeba a 0.3 2.7 5.2 ns t phz , t plz 0.3 2.5 5.2 symbol from to min typ max unit (input) (output) (note 13) t oslh (note 14) a b 0.8 1.0 ns t oshl (note 14) 0.3 0.5 ns t pv(hl) (note 15)(note 16) a b 0.8 ns t oslh (note 14) clkab b 0.9 1.0 ns t oshl (note 14) 0.3 0.5 ns t pv(hl) (note 15)(note 16) clkab b 0.8 ns t oslh (note 14) b a 0.7 1.0 ns t oshl (note 14) 0.6 1.0 ns t ost (note 14) b a 0.7 1.1 ns t pv (note 15) b a 1.5 ns t oslh (note 14) clkab a 0.5 1.0 ns t oshl (note 14) 0.6 1.0 ns t ost (note 14) clkab a 1.1 1.2 ns t pv (note 15) clkab a 1.5 ns
7 www.fairchildsemi.com gtlp18t612 test circuits and timing waveforms test circuit for a outputs note a: c l includes probes and jig capacitance. test circuit for b outputs note b: for b port, c l = 30 pf is used for worst case. voltage waveform - propagation delay times voltage waveform - setup and hold times voltage waveform - pulse width voltage waveform - enable and disable times output waveform 1 is for an output with internal conditions such that the output is low except when disabled by the control output. output waveform 2 is for an output with internal conditions such that the output is high except when disabled by the control output. input and measure conditions all input pulses have the following characteristics: frequency = 10mhz, t rise = t fall = 2 ns (10% to 90%), z o = 50 ? . the outputs are measured one at a time with one transition per measurement. test s t plh /t phl open t plz /t pzl 6v t phz /t pzh gnd a or lvttl pins b or gtlp pins v inhigh 3.0 1.5 v inlow 0.0 0.0 v m 1.5 1.0 v x v ol + 0.3v n/a v y v oh ? 0.3v n/a
www.fairchildsemi.com 8 gtlp18t612 physical dimensions inches (millimeters) unless otherwise noted 54-ball fine-pitch ball grid array (fbga), jedec mo-205, 5.5mm wide package number bga54a
9 www.fairchildsemi.com gtlp18t612 physical dimensions inches (millimeters) unless otherwise noted (continued) 56-lead shrink small outline package (ssop), jedec mo-118, 0.300" wide package number ms56a
www.fairchildsemi.com 10 gtlp18t612 18-bit lvttl/gtlp universal bus transceiver physical dimensions inches (millimeters) unless otherwise noted (continued) 56-lead thin shrink small outline package (tssop), jedec mo-153, 6.1mm wide package number mtd56 fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and fairchild reserves the right at any time without notice to change said circuitry and specifications. life support policy fairchild ? s products are not authorized for use as critical components in life support devices or systems without the express written approval of the president of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be rea- sonably expected to result in a significant injury to the user. 2. a critical component in any component of a life support device or system whose failure to perform can be rea- sonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com
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